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authorshubhrajyoti.datta@xilinx.com <shubhrajyoti.datta@xilinx.com>2016-08-16 10:14:50 +0530
committerDavid S. Miller <davem@davemloft.net>2016-08-18 20:58:42 -0700
commitaead88bd0e990540c03df8108671c93b35354736 (patch)
treeb74ba246bf7717f032439c66b7c773288866f12c /Documentation/devicetree/bindings/net
parentd52bfbda774a9996e0687511ab7a9cd67d195d05 (diff)
net: ethernet: macb: Add support for rx_clk
Some of the platforms like zynqmp ultrascale+ has a separate clock gate for the rx clock. Add an optional rx_clk so that the clock can be enabled. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/net')
-rw-r--r--Documentation/devicetree/bindings/net/macb.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index b5a42df4c928..1506e948610c 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -21,6 +21,7 @@ Required properties:
- clock-names: Tuple listing input clock names.
Required elements: 'pclk', 'hclk'
Optional elements: 'tx_clk'
+ Optional elements: 'rx_clk' applies to cdns,zynqmp-gem
- clocks: Phandles to input clocks.
Optional properties for PHY child node: