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authorDongpo Li <lidongpo@hisilicon.com>2016-07-15 16:26:35 +0800
committerDavid S. Miller <davem@davemloft.net>2016-07-16 21:32:58 -0700
commit542ae60af24f02e130e62cb3b7c23163a2350056 (patch)
treebbbaec56e8e29803470a81e869a6fd2ccd9c0762 /Documentation/devicetree/bindings/net
parentb786241253041c13d94309ca4dace301833f63d1 (diff)
net: hisilicon: Add Fast Ethernet MAC driver
This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver. The FEMAC supports max speed 100Mbps and has been used in many Hisilicon SoC. Signed-off-by: Dongpo Li <lidongpo@hisilicon.com> Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/net')
-rw-r--r--Documentation/devicetree/bindings/net/hisilicon-femac.txt39
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diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
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+++ b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
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+Hisilicon Fast Ethernet MAC controller
+
+Required properties:
+- compatible: should contain one of the following version strings:
+ * "hisilicon,hisi-femac-v1"
+ * "hisilicon,hisi-femac-v2"
+ and the soc string "hisilicon,hi3516cv300-femac".
+- reg: specifies base physical address(s) and size of the device registers.
+ The first region is the MAC core register base and size.
+ The second region is the global MAC control register.
+- interrupts: should contain the MAC interrupt.
+- clocks: A phandle to the MAC main clock.
+- resets: should contain the phandle to the MAC reset signal(required) and
+ the PHY reset signal(optional).
+- reset-names: should contain the reset signal name "mac"(required)
+ and "phy"(optional).
+- mac-address: see ethernet.txt [1].
+- phy-mode: see ethernet.txt [1].
+- phy-handle: see ethernet.txt [1].
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
+
+[1] Documentation/devicetree/bindings/net/ethernet.txt
+
+Example:
+ hisi_femac: ethernet@10090000 {
+ compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
+ reg = <0x10090000 0x1000>,<0x10091300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3518EV200_ETH_CLK>;
+ resets = <&crg 0xec 0>,<&crg 0xec 3>;
+ reset-names = "mac","phy";
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "mii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays-us = <10000 20000 20000>;
+ };