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authorStuart Yoder <stuart.yoder@nxp.com>2016-12-15 18:16:13 -0600
committerRob Herring <robh@kernel.org>2017-01-09 10:19:15 -0600
commit5bb61d14b98bbdd515603604c9167db06f1f2eb2 (patch)
tree6a4498a818d35978b698e8307d1cb4ad49c97ede /Documentation/devicetree/bindings/iommu/arm,smmu.txt
parent33ec224045b70b213f0d0f280dc7e543d71a4763 (diff)
Docs: dt: Be explicit and consistent in reference to IOMMU specifiers
The generic IOMMU binding says that the meaning of an 'IOMMU specifier' is defined by the binding of a specific SMMU. The ARM SMMU binding never explicitly uses the term 'specifier' at all. Update implicit references to use the explicit term. In the iommu-map binding change references to iommu-specifier to "IOMMU specifier" so we are 100% consistent everywhere with terminology and capitalization. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu/arm,smmu.txt')
-rw-r--r--Documentation/devicetree/bindings/iommu/arm,smmu.txt10
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index e862d1485205..6cdf32d037fc 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -36,15 +36,15 @@ conditions.
combined interrupt, it must be listed multiple times.
- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
- for details. With a value of 1, each "iommus" entry
+ for details. With a value of 1, each IOMMU specifier
represents a distinct stream ID emitted by that device
into the relevant SMMU.
SMMUs with stream matching support and complex masters
- may use a value of 2, where the second cell represents
- an SMR mask to combine with the ID in the first cell.
- Care must be taken to ensure the set of matched IDs
- does not result in conflicts.
+ may use a value of 2, where the second cell of the
+ IOMMU specifier represents an SMR mask to combine with
+ the ID in the first cell. Care must be taken to ensure
+ the set of matched IDs does not result in conflicts.
** System MMU optional properties: