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authorSergej Sawazki <sergej@taudac.com>2017-09-16 13:44:41 +0200
committerStephen Boyd <sboyd@codeaurora.org>2017-12-21 18:09:18 -0800
commit51279ef9f64cf7eb8b3f891a2b60fa1aa4938afc (patch)
tree8406d6a2eb541671c99e636161023430a01054df /Documentation/devicetree/bindings/clock/silabs,si5351.txt
parent758231d5a80a784d60ce7c96b27f8771ca4c682b (diff)
clk: si5351: Add DT property to enable PLL reset
Add optional output clock DT property to enable PLL reset when a clock output is enabled. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/silabs,si5351.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/silabs,si5351.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
index a6c4ef343b44..f00191cad8cd 100644
--- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
@@ -49,6 +49,7 @@ Optional child node properties:
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
+- silabs,pll-reset: boolean, clock output can reset its pll.
- silabs,disable-state : clock output disable state, shall be
0 = clock output is driven LOW when disabled
1 = clock output is driven HIGH when disabled