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| author | Stephen Boyd <sboyd@kernel.org> | 2019-09-19 15:31:59 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-09-19 15:31:59 -0700 |
| commit | ebd47c8434064687ab6641e837144e0a3ea3872d (patch) | |
| tree | 2f0eb327eb76cf9e800164f277277d44545ee7c5 /Documentation/devicetree/bindings/arm/mediatek.yaml | |
| parent | b6c444de05acb10c6497549d1d0c6fb7e5883742 (diff) | |
| parent | 7f81c2426587b34bf73e643c1a6d080dfa14cf8a (diff) | |
| parent | 81a6b601f9f49be4e5972c351ad27cb13265c225 (diff) | |
| parent | 5e75ea9c67433a065b0e8595ad3c91c7c0ca0d2d (diff) | |
Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-next
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
* clk-bulk-fix:
clk: Make clk_bulk_get_all() return a valid "id"
* clk-at91:
clk: at91: allow 24 Mhz clock as input for PLL
clk: at91: select parent if main oscillator or bypass is enabled
clk: at91: fix update bit maps on CFG_MOR write
* clk-sprd:
clk: sprd: add missing kfree