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authorWong, Vee Khee <vee.khee.wong@intel.com>2021-03-26 01:39:16 +0800
committerDavid S. Miller <davem@davemloft.net>2021-03-25 17:37:30 -0700
commit6ccf12ae111e49324b439410066e8cc359aeee6d (patch)
tree1c268024e10fcf3e50158107d46348d624c3ed23 /Documentation/accounting
parentb42446b9b37ba444ba12d89dd9d45c2b68768f24 (diff)
net: stmmac: use interrupt mode INTM=1 for multi-MSI
For interrupt mode INTM=0, TX/RX transfer complete will trigger signal not only on sbd_perch_[tx|rx]_intr_o (Transmit/Receive Per Channel) but also on the sbd_intr_o (Common). As for multi-MSI implementation, setting interrupt mode INTM=1 is more efficient as each TX intr and RX intr (TI/RI) will be handled by TX/RX ISR without the need of calling the common MAC ISR. Updated the TX/RX NORMAL interrupts status checking process as the NIS status bit is not asserted for any RI/TI events for INTM=1. Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com> Co-developed-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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