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authorBenjamin Gaignard <benjamin.gaignard@linaro.org>2017-01-20 10:15:07 +0100
committerLee Jones <lee.jones@linaro.org>2017-01-25 16:11:56 +0000
commit93fbe91b552194af970256ce72934745d01df435 (patch)
treefd34fba1c4fac1a69cf17927f4e316b891822d50 /Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
parentbf2d8581b1b3ddd72a679e06157b57c1e2dd7b23 (diff)
iio: Add STM32 timer trigger driver
Timers IPs can be used to generate triggers for other IPs like DAC or ADC. Each trigger may result of timer internals signals like counter enable, reset or edge, this configuration could be done through "master_mode" device attribute. Since triggers could be used by DAC or ADC their names are defined in include/ nux/iio/timer/stm32-timer-trigger.h and is_stm32_iio_timer_trigger function could be used to check if the trigger is valid or not. "trgo" trigger have a "sampling_frequency" attribute which allow to configure timer sampling frequency. version 8: - change kernel version from 4.10 to 4.11 in ABI documentation version 7: - remove all iio_device related code - move driver into trigger directory version 5: - simplify tables of triggers - only create an IIO device when needed version 4: - get triggers configuration from "reg" in DT - add tables of triggers - sampling frequency is enable/disable when writing in trigger sampling_frequency attribute - no more use of interruptions version 3: - change compatible to "st,stm32-timer-trigger" - fix attributes access right - use string instead of int for master_mode and slave_mode - document device attributes in sysfs-bus-iio-timer-stm32 version 2: - keep only one compatible - use st,input-triggers-names and st,output-triggers-names to know which triggers are accepted and/or create by the device Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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+What: /sys/bus/iio/devices/triggerX/master_mode_available
+KernelVersion: 4.11
+Contact: benjamin.gaignard@st.com
+Description:
+ Reading returns the list possible master modes which are:
+ - "reset" : The UG bit from the TIMx_EGR register is used as trigger output (TRGO).
+ - "enable" : The Counter Enable signal CNT_EN is used as trigger output.
+ - "update" : The update event is selected as trigger output.
+ For instance a master timer can then be used as a prescaler for a slave timer.
+ - "compare_pulse" : The trigger output send a positive pulse when the CC1IF flag is to be set.
+ - "OC1REF" : OC1REF signal is used as trigger output.
+ - "OC2REF" : OC2REF signal is used as trigger output.
+ - "OC3REF" : OC3REF signal is used as trigger output.
+ - "OC4REF" : OC4REF signal is used as trigger output.
+
+What: /sys/bus/iio/devices/triggerX/master_mode
+KernelVersion: 4.11
+Contact: benjamin.gaignard@st.com
+Description:
+ Reading returns the current master modes.
+ Writing set the master mode
+
+What: /sys/bus/iio/devices/triggerX/sampling_frequency
+KernelVersion: 4.11
+Contact: benjamin.gaignard@st.com
+Description:
+ Reading returns the current sampling frequency.
+ Writing an value different of 0 set and start sampling.
+ Writing 0 stop sampling.