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authorPaul Burton <paul.burton@imgtec.com>2013-12-02 16:48:37 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-23 13:02:35 +0100
commitae0d7cbc99890b3a417a5705763784b8551a10d6 (patch)
tree5cad4268f616744749f6ea23e5ce406ecd2aec35 /CREDITS
parenta87ea88d8f6c7ce5551b3761f8db5a4341c8b25d (diff)
MIPS: Malta: mux & enable SERIRQ interrupt
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
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