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authorRodrigo Vivi <rodrigo.vivi@intel.com>2017-06-09 15:26:14 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2017-06-12 09:46:21 -0700
commitff15947e0f02ceccfffa8f342472765404d161b6 (patch)
tree16f7eac5a36537a064e253a88a3b69012f2f1b59
parent4efa16cae0629faa2f5f0e7d089c1b85d946805a (diff)
drm/i915/cnl: LSPCON support is gen9+
There is no platform specific change needed for LSPCON support on Cannonlake. So let's make it gen9+. Cc: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd22f3d0d9d6..c3ea485cb82a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3002,7 +3002,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
-#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
+#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)