diff options
| author | Danielle Ratson <danieller@nvidia.com> | 2021-03-10 13:02:18 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-03-10 13:04:57 -0800 |
| commit | ff12ba3ad78db47f8c824841259c7cc188f37f19 (patch) | |
| tree | fd850c7f42eef408622caf93dec051f02be626c5 | |
| parent | 2ab781c2ccf477012489e30ad0f1c1aa42398437 (diff) | |
mlxsw: reg: Extend MFDE register with new log_ip field
Extend MFDE (Monitoring FW Debug) register with new field specifying the
instruction pointer that triggered the CR space timeout.
Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index afd42907092f..a042ff79d306 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -10979,6 +10979,13 @@ MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); */ MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); +/* reg_mfde_log_ip + * IP (instruction pointer) that triggered the timeout. + * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO + * Access: RO + */ +MLXSW_ITEM64(reg, mfde, log_ip, 0x18, 0, 64); + /* reg_mfde_pipes_mask * Bit per kvh pipe. * Access: RO |