diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-08-19 14:49:26 +0900 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-08-20 18:28:39 -0700 |
| commit | f2032f24c0e51487d88c3555db12e27d561e4f14 (patch) | |
| tree | d7b2cf20932073c6c7589a4d2b94dddffaaf2166 | |
| parent | 62060a3548c5ea038b4ade518cce92be32a6718d (diff) | |
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi index ccf795ab96b2..4c7b24611012 100644 --- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi @@ -249,14 +249,14 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; + interrupts = <1 11 0xf04>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <1 13 0xf04>; clocks = <&arm_timer_clk>; }; |