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authorMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>2018-11-07 15:41:26 +0200
committerMark Brown <broonie@kernel.org>2018-11-13 16:27:05 -0800
commite770b18bbbaecebfb37389b45bf82974a17488d7 (patch)
tree0d084d887d50d30aa96a5db438614724bf12a028
parentef4de050b4c796ef13421032403ad986c00423d3 (diff)
regulator: bd718x7: Change next state after poweroff to ready
BD71837 and BD71847 have a HW functionality which leave power rails OFF after powerof state: - if they have been controlled by SW. - if state transition from poweroff is done to SNVS BD71837 can after reset transition from power-off to SNVS or READY state depending on reset reason. By default only wathcdog reset changes state from poweroff to ready. Change PMIC configuration to always transition to READY in order to avoid crucial power rails being OFF after reset. If SNVS is required the crucial power rails should not be controlled by SW - eg corresponding regulator control register should have SEL bit kept zero. Currently the driver assumes all regulators to be controlled by SW so it sets all SEL bits to 1. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/regulator/bd718x7-regulator.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/regulator/bd718x7-regulator.c b/drivers/regulator/bd718x7-regulator.c
index 512c936ae021..e63581651d69 100644
--- a/drivers/regulator/bd718x7-regulator.c
+++ b/drivers/regulator/bd718x7-regulator.c
@@ -1054,6 +1054,29 @@ static int bd718xx_probe(struct platform_device *pdev)
BD718XX_REG_REGLOCK);
}
+ /* At poweroff transition PMIC HW disables EN bit for regulators but
+ * leaves SEL bit untouched. So if state transition from POWEROFF
+ * is done to SNVS - then all power rails controlled by SW (having
+ * SEL bit set) stay disabled as EN is cleared. This may result boot
+ * failure if any crucial systems are powered by these rails.
+ *
+ * Change the next stage from poweroff to be READY instead of SNVS
+ * for all reset types because OTP loading at READY will clear SEL
+ * bit allowing HW defaults for power rails to be used
+ */
+ err = regmap_update_bits(mfd->regmap, BD718XX_REG_TRANS_COND1,
+ BD718XX_ON_REQ_POWEROFF_MASK |
+ BD718XX_SWRESET_POWEROFF_MASK |
+ BD718XX_WDOG_POWEROFF_MASK |
+ BD718XX_KEY_L_POWEROFF_MASK,
+ BD718XX_POWOFF_TO_RDY);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to change reset target\n");
+ goto err;
+ } else {
+ dev_dbg(&pdev->dev, "Changed all resets from SVNS to READY\n");
+ }
+
for (i = 0; i < pmic_regulators[mfd->chip_type].r_amount; i++) {
const struct regulator_desc *desc;