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authorJavier Cardona <javier@cozybit.com>2008-02-08 18:41:17 -0800
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:37:13 -0500
commite51c683717e3ac21713444e9a517aa8e0ad0ee48 (patch)
tree5082d6cdb12714410a1ba73c0bc234352e664005
parent9f6adf23d87ad394ed03c038409550ca37029154 (diff)
zd1211rw: Fixed incorrect constant name.
Trial and error reveals that CR_ZD1211B_TX_PWR_CTL* do not affect the transmission power. Instead these registers seem to control the contention windows limits for different QoS access categories. Signed-off-by: Javier Cardona <javier@cozybit.com> Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.c8
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.h9
2 files changed, 8 insertions, 9 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index e3fba6f09455..db96adf90ae2 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -771,10 +771,10 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip)
{
static const struct zd_ioreq32 ioreqs[] = {
{ CR_ZD1211B_RETRY_MAX, 0x02020202 },
- { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
- { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
- { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
- { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
+ { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
+ { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
+ { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
+ { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
{ CR_ZD1211B_AIFS_CTL1, 0x00280028 },
{ CR_ZD1211B_AIFS_CTL2, 0x008C003C },
{ CR_ZD1211B_TXOP, 0x01800824 },
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
index 009c03777a35..5b6e3a3751ba 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.h
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -625,11 +625,10 @@ enum {
#define CR_S_MD CTL_REG(0x0830)
#define CR_USB_DEBUG_PORT CTL_REG(0x0888)
-
-#define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00)
-#define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04)
-#define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08)
-#define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c)
+#define CR_ZD1211B_CWIN_MAX_MIN_AC0 CTL_REG(0x0b00)
+#define CR_ZD1211B_CWIN_MAX_MIN_AC1 CTL_REG(0x0b04)
+#define CR_ZD1211B_CWIN_MAX_MIN_AC2 CTL_REG(0x0b08)
+#define CR_ZD1211B_CWIN_MAX_MIN_AC3 CTL_REG(0x0b0c)
#define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10)
#define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14)
#define CR_ZD1211B_TXOP CTL_REG(0x0b20)