diff options
author | Arnd Bergmann <arnd@arndb.de> | 2017-10-30 15:55:12 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-30 15:55:12 +0100 |
commit | da984d754069818090511fc3b36ea2f9a0b538b5 (patch) | |
tree | 2042448aac1ada99850430d35ba659a177f87ba0 | |
parent | 36a247ba728b68383e53b4cf11111801ec3ceecd (diff) | |
parent | cda80a82ac3e89309706c027ada6ab232be1d640 (diff) |
Merge tag 'mvebu-fixes-4.14-3' of git://git.infradead.org/linux-mvebu into fixes
Pull "mvebu fixes for 4.14 (part 3)" from Gregory CLEMENT:
Fixing an old stability issue on Cortex A9 based mvebu SoC
* tag 'mvebu-fixes-4.14-3' of git://git.infradead.org/linux-mvebu:
ARM: dts: mvebu: pl310-cache disable double-linefill
-rw-r--r-- | arch/arm/boot/dts/armada-375.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-39x.dtsi | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 7225c7ce9a8d..2cb1bcd30976 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -178,9 +178,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; - arm,double-linefill-incr = <1>; + arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; - arm,double-linefill = <1>; + arm,double-linefill = <0>; prefetch-data = <1>; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 4960722aab32..00ff549d4e39 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -143,9 +143,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; - arm,double-linefill-incr = <1>; + arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; - arm,double-linefill = <1>; + arm,double-linefill = <0>; prefetch-data = <1>; }; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index ea657071e278..5218bd2a248d 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -111,9 +111,9 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; - arm,double-linefill-incr = <1>; + arm,double-linefill-incr = <0>; arm,double-linefill-wrap = <0>; - arm,double-linefill = <1>; + arm,double-linefill = <0>; prefetch-data = <1>; }; |