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authorRob Herring <robh@kernel.org>2020-08-20 21:54:18 -0600
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2020-09-10 16:50:53 +0100
commitd439e7edd1343ead0150851ca78055858ee8b94e (patch)
treebbc32ca20c1ec1eaf4b18929e9b15965a882982f
parentcf854be2d9a34665cbbd40d58409fc868ed476fc (diff)
PCI: dwc/intel-gw: Drop unused max_width
'max_width' is read, but never used, so let's remove it. Link: https://lore.kernel.org/r/20200821035420.380495-39-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Dilip Kota <eswara.kota@linux.intel.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/controller/dwc/pcie-intel-gw.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 807e1fa1bd6f..333f11561807 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -67,7 +67,6 @@ struct intel_pcie_port {
void __iomem *app_base;
struct gpio_desc *reset_gpio;
u32 rst_intrvl;
- u32 max_width;
u32 n_fts;
struct clk *core_clk;
struct reset_control *core_rst;
@@ -133,9 +132,6 @@ static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
u32 val;
u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
- val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCAP);
- lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
-
val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCTL);
val &= ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC);