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author | Alex Deucher <alexander.deucher@amd.com> | 2020-06-03 13:59:16 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:15 -0400 |
commit | cb8bcc98251b88dbf5ddd6427971d8e7b298ce75 (patch) | |
tree | f4a7857e19c240cb74d216cf97ecf052fa04bbee | |
parent | f0bfa78b0f721b8c2ba60eaa74b784e3f30181f7 (diff) |
drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0
Need to guard some new DCN3.0 stuff.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index 43d0b4e53b5d..2972392f9788 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -288,13 +288,16 @@ void optc1_program_timing( if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) h_div = H_TIMING_DIV_BY2; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { if (optc1->opp_count == 4) h_div = H_TIMING_DIV_BY4; REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, h_div); - } else { + } else +#endif + { REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, h_div); } |