diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2016-10-20 13:42:55 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2016-10-20 10:18:25 -0700 |
| commit | caafa69d364f922428240dd9e30ae6ae303abc97 (patch) | |
| tree | ff499eeb829776fa8b3d1055266dc0a6365a211e | |
| parent | ef8d2ffedf1878e4dc8d19d83371cef8e2457a44 (diff) | |
ARM64: dts: meson-gxbb: Add Wifi 32K clock for p20x boards
Add a 32768Hz clock generated by the PWM E port used by the WiFi module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 86e740fb5969..6861b0af6573 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -111,6 +111,13 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; }; /* This UART is brought out to the DB9 connector */ @@ -205,3 +212,11 @@ vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vddio_boot>; }; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; |