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authorBoyuan Zhang <boyuan.zhang@amd.com>2020-07-01 17:59:51 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-15 12:47:14 -0400
commitc6e9dd0ea8355024de890f559b78c83a365641d0 (patch)
tree96d91d11788df920c3337e48acc8cebbcd47ad64
parentebb06097ee29442461f9b3bcd745d85e6fa9996b (diff)
drm/amdgpu: enable VCN3.0 DPG for navy_flounder
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 13efe87c7a75..7f2af248254e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -776,7 +776,8 @@ static int nv_common_early_init(void *handle)
break;
case CHIP_NAVY_FLOUNDER:
adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG;
- adev->pg_flags = AMD_PG_SUPPORT_VCN;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 0x32;
break;