diff options
| author | Robert Jarzmik <robert.jarzmik@free.fr> | 2016-10-17 21:45:32 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-10-18 14:14:21 -0400 |
| commit | c4055a8cf7ba0042947309d1eada4d842bd3d8b7 (patch) | |
| tree | 3cd14a3eabd49dbdbc4684043985dbb22bf2337a | |
| parent | 9c365f31775c43462e431bf5ff3c569190a1a08f (diff) | |
net: smsc91x: add u16 workaround for pxa platforms
Add a workaround for mainstone, idp and stargate2 boards, for u16 writes
which must be aligned on 32 bits addresses.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | Documentation/devicetree/bindings/net/smsc-lan91c111.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt index e77e167593db..309e37eb7c7c 100644 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt @@ -13,3 +13,5 @@ Optional properties: 16-bit access only. - power-gpios: GPIO to control the PWRDWN pin - reset-gpios: GPIO to control the RESET pin +- pxa-u16-align4 : Boolean, put in place the workaround the force all + u16 writes to be 32 bits aligned |