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authorFabio Estevam <fabio.estevam@nxp.com>2017-06-06 12:45:54 -0300
committerStephen Boyd <sboyd@codeaurora.org>2017-06-06 17:42:41 -0700
commitb608a89221b401d7b07a1b6330777a034d204410 (patch)
treeaf312909fcc2f3eece898d1b098fb08c4738d16a
parent4a5f06a01cfd1f7a9141bdb760bf5b68cca7f224 (diff)
clk: imx7d: Fix the DDR PLL enable bit
Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case. Fix it accordingly to avoid a kernel hang. Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/imx/clk-pllv3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 0039b169364e..9af62ee8f347 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -453,7 +453,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
ops = &clk_pllv3_enet_ops;
break;
case IMX_PLLV3_DDR_IMX7:
- pll->power_bit = IMX7_ENET_PLL_POWER;
+ pll->power_bit = IMX7_DDR_PLL_POWER;
ops = &clk_pllv3_av_ops;
break;
default: