diff options
| author | Imre Deak <imre.deak@intel.com> | 2021-05-24 20:27:01 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-05-25 13:06:07 +0300 |
| commit | b3de1d0789197935da054e47952694adc8219203 (patch) | |
| tree | 1060c5eb165fbda94da250c7b22c2f25cbc097db | |
| parent | 6f20785b760119dfc9e5ad569110a9b0e6b3fe35 (diff) | |
drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
All DPT FB color plane surface base addresses must be 2MB aligned. On
ADL_P this means that the offsets in CCS FB object must be also 2MB
aligned. Adjusting unaligned offsets for these FBs during commit time
(compensating with the x/y offsets) doesn't work, since the big
alignment would most probably lead to an x/y offset mismatch error
between the main and CCS planes.
We can overcome this limitation by remapping CCS FBs, so that each color
plane is at an aligned offset, leaving x/y for each plane unadjusted
during commit and so not causing an x/y mismatch error. However
remapping for CCS FBs will be done as a follow-up, so for now require
that user space allocates the FB obj with properly aligned planes.
v2: s/SZ_2M/512*4k/ for clarity. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210524172703.2113058-1-imre.deak@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fb.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a005c68889e7..c60a81a81c09 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -355,8 +355,17 @@ static int intel_fb_offset_to_xy(int *x, int *y, unsigned int height; u32 alignment; - if (DISPLAY_VER(i915) >= 12 && - is_semiplanar_uv_plane(fb, color_plane)) + /* + * All DPT color planes must be 512*4k aligned (the amount mapped by a + * single DPT page). For ADL_P CCS FBs this only works by requiring + * the allocated offsets to be 2MB aligned. Once supoort to remap + * such FBs is added we can remove this requirement, as then all the + * planes can be remapped to an aligned offset. + */ + if (IS_ALDERLAKE_P(i915) && is_ccs_modifier(fb->modifier)) + alignment = 512 * 4096; + else if (DISPLAY_VER(i915) >= 12 && + is_semiplanar_uv_plane(fb, color_plane)) alignment = intel_tile_row_size(fb, color_plane); else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) alignment = intel_tile_size(i915); |