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authorDamien Lespiau <damien.lespiau@intel.com>2015-01-20 12:51:50 +0000
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-01-27 09:51:03 +0100
commitb35d63fae6a2a3a0e1949228de07f795a73f23d0 (patch)
tree4ae52e9cc90b54937da56660d8c0a5a6b28b9626
parenta55ecbe339846d883c860fb2143a77ea4c47e7b8 (diff)
drm/i915/skl: intel_format_to_fourcc() doesn't work for SKL planes
We will have a skl_ version shortly! Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95bb420f61e7..bd5b9a6e3a0e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2316,7 +2316,7 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
}
}
-static int intel_format_to_fourcc(int format)
+static int i9xx_format_to_fourcc(int format)
{
switch (format) {
case DISPPLANE_8BPP:
@@ -6569,7 +6569,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
- fourcc = intel_format_to_fourcc(pixel_format);
+ fourcc = i9xx_format_to_fourcc(pixel_format);
fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
@@ -7621,7 +7621,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
plane_config->tiling = I915_TILING_X;
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
- fourcc = intel_format_to_fourcc(pixel_format);
+ fourcc = i9xx_format_to_fourcc(pixel_format);
fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;