edac.txt: convert EDAC documentation to ReST

Converts the EDAC driver subsystem documentation to ReST:

- Put paragraph titles in lower case;
- Add code blocks where needed;
- Convert tables to ReST markup;
- Mark filesystem and module names as verbatim;
- Adjust document to be properly displayed in html.

Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>

1 files changed, 295 insertions, 256 deletions

diff --git a/Documentation/edac.txt b/Documentation/edac.txt
index 502988524519..316456ba2e0a 100644
--- a/Documentation/edac.txt
+++ b/Documentation/edac.txt
@@ -1,29 +1,34 @@
+.. include:: <isonum.txt>
+
+=====================================
 EDAC - Error Detection And Correction
 =====================================
 
-"bluesmoke" was the name for this device driver when it
-was "out-of-tree" and maintained at sourceforge.net -
-bluesmoke.sourceforge.net. That site is mostly archaic now and can be
-used only for historical purposes.
+.. note::
 
-When the subsystem was pushed into 2.6.16 for the first time, it was
-renamed to 'EDAC'.
+   "bluesmoke" was the name for this device driver when it
+   was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net.
+   That site is mostly archaic now and can be used only for historical
+   purposes.
 
-PURPOSE
+   When the subsystem was pushed into 2.6.16 for the first time, it was
+   renamed to ``EDAC``.
+
+Purpose
 -------
 
-The 'edac' kernel module's goal is to detect and report hardware errors
+The ``edac`` kernel module's goal is to detect and report hardware errors
 that occur within the computer system running under linux.
 
-MEMORY
+Memory
 ------
 
 Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the
 primary errors being harvested. These types of errors are harvested by
-the 'edac_mc' device.
+the ``edac_mc`` device.
 
 Detecting CE events, then harvesting those events and reporting them,
-*can* but must not necessarily be a predictor of future UE events. With
+**can** but must not necessarily be a predictor of future UE events. With
 CE events only, the system can and will continue to operate as no data
 has been damaged yet.
 
@@ -31,10 +36,10 @@ However, preventive maintenance and proactive part replacement of memory
 DIMMs exhibiting CEs can reduce the likelihood of the dreaded UE events
 and system panics.
 
-OTHER HARDWARE ELEMENTS
+Other hardware elements
 -----------------------
 
-A new feature for EDAC, the edac_device class of device, was added in
+A new feature for EDAC, the ``edac_device`` class of device, was added in
 the 2.6.23 version of the kernel.
 
 This new device type allows for non-memory type of ECC hardware detectors
@@ -48,14 +53,14 @@ reports it, then a edac_device device probably can be constructed to
 harvest and present that to userspace.
 
 
-PCI BUS SCANNING
+PCI bus scanning
 ----------------
 
 In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors
 in order to determine if errors are occurring during data transfers.
 
 The presence of PCI Parity errors must be examined with a grain of salt.
-There are several add-in adapters that do *not* follow the PCI specification
+There are several add-in adapters that do **not** follow the PCI specification
 with regards to Parity generation and reporting. The specification says
 the vendor should tie the parity status bits to 0 if they do not intend
 to generate parity.  Some vendors do not do this, and thus the parity bit
@@ -63,62 +68,64 @@ can "float" giving false positives.
 
 There is a PCI device attribute located in sysfs that is checked by
 the EDAC PCI scanning code. If that attribute is set, PCI parity/error
-scanning is skipped for that device. The attribute is:
+scanning is skipped for that device. The attribute is::
 
 	broken_parity_status
 
-and is located in /sys/devices/pci<XXX>/0000:XX:YY.Z directories for
+and is located in ``/sys/devices/pci<XXX>/0000:XX:YY.Z`` directories for
 PCI devices.
 
 
-VERSIONING
+Versioning
 ----------
 
-EDAC is composed of a "core" module (edac_core.ko) and several Memory
+EDAC is composed of a "core" module (``edac_core.ko``) and several Memory
 Controller (MC) driver modules. On a given system, the CORE is loaded
 and one MC driver will be loaded. Both the CORE and the MC driver (or
-edac_device driver) have individual versions that reflect current
+``edac_device`` driver) have individual versions that reflect current
 release level of their respective modules.
 
 Thus, to "report" on what version a system is running, one must report
 both the CORE's and the MC driver's versions.
 
 
-LOADING
+Loading
 -------
 
-If 'edac' was statically linked with the kernel then no loading
-is necessary. If 'edac' was built as modules then simply modprobe
-the 'edac' pieces that you need. You should be able to modprobe
+If ``edac`` was statically linked with the kernel then no loading
+is necessary. If ``edac`` was built as modules then simply modprobe
+the ``edac`` pieces that you need. You should be able to modprobe
 hardware-specific modules and have the dependencies load the necessary
 core modules.
 
-Example:
+Example::
 
-$> modprobe amd76x_edac
+	$ modprobe amd76x_edac
 
-loads both the amd76x_edac.ko memory controller module and the edac_mc.ko
-core module.
+loads both the ``amd76x_edac.ko`` memory controller module and the
+``edac_mc.ko`` core module.
 
 
-SYSFS INTERFACE
+Sysfs interface
 ---------------
 
-EDAC presents a 'sysfs' interface for control and reporting purposes. It
+EDAC presents a ``sysfs`` interface for control and reporting purposes. It
 lives in the /sys/devices/system/edac directory.
 
 Within this directory there currently reside 2 components:
 
+	======= ==============================
 	mc	memory controller(s) system
 	pci	PCI control and status system
+	======= ==============================
 
 
 
 Memory Controller (mc) Model
 ----------------------------
 
-Each 'mc' device controls a set of DIMM memory modules. These modules
-are laid out in a Chip-Select Row (csrowX) and Channel table (chX).
+Each ``mc`` device controls a set of DIMM memory modules. These modules
+are laid out in a Chip-Select Row (``csrowX``) and Channel table (``chX``).
 There can be multiple csrows and multiple channels.
 
 Memory controllers allow for several csrows, with 8 csrows being a
@@ -129,28 +136,28 @@ Dual channels allows for 128 bit data transfers to/from the CPU from/to
 memory. Some newer chipsets allow for more than 2 channels, like Fully
 Buffered DIMMs (FB-DIMMs). The following example will assume 2 channels:
 
-
-		Channel 0	Channel 1
-	===================================
-	csrow0	| DIMM_A0	| DIMM_B0 |
-	csrow1	| DIMM_A0	| DIMM_B0 |
-	===================================
-
-	===================================
-	csrow2	| DIMM_A1	| DIMM_B1 |
-	csrow3	| DIMM_A1	| DIMM_B1 |
-	===================================
+	+--------+-----------+-----------+
+	|        | Channel 0 | Channel 1 |
+	+========+===========+===========+
+	| csrow0 |  DIMM_A0  |  DIMM_B0  |
+	+--------+           |           |
+	| csrow1 |           |           |
+	+--------+-----------+-----------+
+	| csrow2 |  DIMM_A1  | DIMM_B1   |
+	+--------+           |           |
+	| csrow3 |           |           |
+	+--------+-----------+-----------+
 
 In the above example table there are 4 physical slots on the motherboard
 for memory DIMMs:
 
-	DIMM_A0
-	DIMM_B0
-	DIMM_A1
-	DIMM_B1
+	- DIMM_A0
+	- DIMM_B0
+	- DIMM_A1
+	- DIMM_B1
 
 Labels for these slots are usually silk-screened on the motherboard.
-Slots labeled 'A' are channel 0 in this example. Slots labeled 'B' are
+Slots labeled ``A`` are channel 0 in this example. Slots labeled ``B`` are
 channel 1. Notice that there are two csrows possible on a physical DIMM.
 These csrows are allocated their csrow assignment based on the slot into
 which the memory DIMM is placed. Thus, when 1 DIMM is placed in each
@@ -166,8 +173,7 @@ csrow3.
 The representation of the above is reflected in the directory
 tree in EDAC's sysfs interface. Starting in directory
 /sys/devices/system/edac/mc each memory controller will be represented
-by its own 'mcX' directory, where 'X' is the index of the MC.
-
+by its own ``mcX`` directory, where ``X`` is the index of the MC::
 
 	..../edac/mc/
 		   |
@@ -176,9 +182,8 @@ by its own 'mcX' directory, where 'X' is the index of the MC.
 		   |->mc2
 		   ....
 
-Under each 'mcX' directory each 'csrowX' is again represented by a
-'csrowX', where 'X' is the csrow index:
-
+Under each ``mcX`` directory each ``csrowX`` is again represented by a
+``csrowX``, where ``X`` is the csrow index::
 
 	.../mc/mc0/
 		|
@@ -194,17 +199,18 @@ csrow3 are populated, this indicates a dual ranked set of DIMMs for
 channels 0 and 1.
 
 
-Within each of the 'mcX' and 'csrowX' directories are several EDAC
+Within each of the ``mcX`` and ``csrowX`` directories are several EDAC
 control and attribute files.
 
 
-'mcX' directories
------------------
+``mcX`` directories
+-------------------
 
-In 'mcX' directories are EDAC control and attribute files for
-this 'X' instance of the memory controllers.
+In ``mcX`` directories are EDAC control and attribute files for
+this ``X`` instance of the memory controllers.
 
 For a description of the sysfs API, please see:
+
 	Documentation/ABI/testing/sysfs-devices-edac
 
 
@@ -329,21 +335,19 @@ this ``X`` memory module:
   symlinks inside the sysfs mapping that are automatically created by
   the sysfs subsystem. Currently, they serve no purpose.
 
-'csrowX' directories
---------------------
+``csrowX`` directories
+----------------------
 
 When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the csrowX
 directories. As this API doesn't work properly for Rambus, FB-DIMMs and
 modern Intel Memory Controllers, this is being deprecated in favor of
 dimmX directories.
 
-In the 'csrowX' directories are EDAC control and attribute files for
-this 'X' instance of csrow:
+In the ``csrowX`` directories are EDAC control and attribute files for
+this ``X`` instance of csrow:
 
 
-Total Uncorrectable Errors count attribute file:
-
-	'ue_count'
+- ``ue_count`` - Total Uncorrectable Errors count attribute file
 
 	This attribute file displays the total count of uncorrectable
 	errors that have occurred on this csrow. If panic_on_ue is set
@@ -351,9 +355,7 @@ Total Uncorrectable Errors count attribute file:
 	will panic the system.
 
 
-Total Correctable Errors count attribute file:
-
-	'ce_count'
+- ``ce_count`` - Total Correctable Errors count attribute file
 
 	This attribute file displays the total count of correctable
 	errors that have occurred on this csrow. This count is very
@@ -363,65 +365,54 @@ Total Correctable Errors count attribute file:
 	to the system administrator.
 
 
-Total memory managed by this csrow attribute file:
-
-	'size_mb'
+- ``size_mb`` - Total memory managed by this csrow attribute file
 
 	This attribute file displays, in count of megabytes, the memory
 	that this csrow contains.
 
 
-Memory Type attribute file:
-
-	'mem_type'
+- ``mem_type`` - Memory Type attribute file
 
 	This attribute file will display what type of memory is currently
 	on this csrow. Normally, either buffered or unbuffered memory.
 	Examples:
-		Registered-DDR
-		Unbuffered-DDR
 
+		- Registered-DDR
+		- Unbuffered-DDR
 
-EDAC Mode of operation attribute file:
 
-	'edac_mode'
+- ``edac_mode`` - EDAC Mode of operation attribute file
 
 	This attribute file will display what type of Error detection
 	and correction is being utilized.
 
 
-Device type attribute file:
-
-	'dev_type'
+- ``dev_type`` - Device type attribute file
 
 	This attribute file will display what type of DRAM device is
 	being utilized on this DIMM.
 	Examples:
-		x1
-		x2
-		x4
-		x8
 
+		- x1
+		- x2
+		- x4
+		- x8
 
-Channel 0 CE Count attribute file:
 
-	'ch0_ce_count'
+- ``ch0_ce_count`` - Channel 0 CE Count attribute file
 
 	This attribute file will display the count of CEs on this
 	DIMM located in channel 0.
 
 
-Channel 0 UE Count attribute file:
-
-	'ch0_ue_count'
+- ``ch0_ue_count`` - Channel 0 UE Count attribute file
 
 	This attribute file will display the count of UEs on this
 	DIMM located in channel 0.
 
 
-Channel 0 DIMM Label control file:
+- ``ch0_dimm_label`` - Channel 0 DIMM Label control file
 
-	'ch0_dimm_label'
 
 	This control file allows this DIMM to have a label assigned
 	to it. With this label in the module, when errors occur
@@ -436,25 +427,21 @@ Channel 0 DIMM Label control file:
 	must occur in userland at this time.
 
 
-Channel 1 CE Count attribute file:
+- ``ch1_ce_count`` - Channel 1 CE Count attribute file
 
-	'ch1_ce_count'
 
 	This attribute file will display the count of CEs on this
 	DIMM located in channel 1.
 
 
-Channel 1 UE Count attribute file:
+- ``ch1_ue_count`` - Channel 1 UE Count attribute file
 
-	'ch1_ue_count'
 
 	This attribute file will display the count of UEs on this
 	DIMM located in channel 0.
 
 
-Channel 1 DIMM Label control file:
-
-	'ch1_dimm_label'
+- ``ch1_dimm_label`` - Channel 1 DIMM Label control file
 
 	This control file allows this DIMM to have a label assigned
 	to it. With this label in the module, when errors occur
@@ -469,33 +456,44 @@ Channel 1 DIMM Label control file:
 	must occur in userland at this time.
 
 
-
-SYSTEM LOGGING
+System Logging
 --------------
 
 If logging for UEs and CEs is enabled, then system logs will contain
-information indicating that errors have been detected:
+information indicating that errors have been detected::
 
-EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0,
-channel 1 "DIMM_B1": amd76x_edac
-
-EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0,
-channel 1 "DIMM_B1": amd76x_edac
+  EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac
+  EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac
 
 
 The structure of the message is:
-	the memory controller			(MC0)
-	Error type				(CE)
-	memory page				(0x283)
-	offset in the page			(0xce0)
-	the byte granularity 			(grain 8)
-		or resolution of the error
-	the error syndrome			(0xb741)
-	memory row				(row 0)
-	memory channel				(channel 1)
-	DIMM label, if set prior		(DIMM B1
-	and then an optional, driver-specific message that may
-		have additional information.
+
+	+---------------------------------------+-------------+
+	| Content                               + Example     |
+	+=======================================+=============+
+	| The memory controller                 | MC0         |
+	+---------------------------------------+-------------+
+	| Error type                            | CE          |
+	+---------------------------------------+-------------+
+	| Memory page                           | 0x283       |
+	+---------------------------------------+-------------+
+	| Offset in the page                    | 0xce0       |
+	+---------------------------------------+-------------+
+	| The byte granularity                  | grain 8     |
+	| or resolution of the error            |             |
+	+---------------------------------------+-------------+
+	| The error syndrome                    | 0xb741      |
+	+---------------------------------------+-------------+
+	| Memory row                            | row 0       +
+	+---------------------------------------+-------------+
+	| Memory channel                        | channel 1   |
+	+---------------------------------------+-------------+
+	| DIMM label, if set prior              | DIMM B1     |
+	+---------------------------------------+-------------+
+	| And then an optional, driver-specific |             |
+	| message that may have additional      |             |
+	| information.                          |             |
+	+---------------------------------------+-------------+
 
 Both UEs and CEs with no info will lack all but memory controller, error
 type, a notice of "no info" and then an optional, driver-specific error
@@ -512,43 +510,38 @@ Type 01 bridges, the secondary status register is also looked at to see
 if parity occurred on the bus on the other side of the bridge.
 
 
-SYSFS CONFIGURATION
+Sysfs configuration
 -------------------
 
-Under /sys/devices/system/edac/pci are control and attribute files as follows:
+Under ``/sys/devices/system/edac/pci`` are control and attribute files as
+follows:
 
 
-Enable/Disable PCI Parity checking control file:
-
-	'check_pci_parity'
-
+- ``check_pci_parity`` - Enable/Disable PCI Parity checking control file
 
 	This control file enables or disables the PCI Bus Parity scanning
 	operation. Writing a 1 to this file enables the scanning. Writing
 	a 0 to this file disables the scanning.
 
-	Enable:
-	echo "1" >/sys/devices/system/edac/pci/check_pci_parity
+	Enable::
+
+		echo "1" >/sys/devices/system/edac/pci/check_pci_parity
 
-	Disable:
-	echo "0" >/sys/devices/system/edac/pci/check_pci_parity
+	Disable::
 
+		echo "0" >/sys/devices/system/edac/pci/check_pci_parity
 
-Parity Count:
 
-	'pci_parity_count'
+- ``pci_parity_count`` - Parity Count
 
 	This attribute file will display the number of parity errors that
 	have been detected.
 
 
-
-MODULE PARAMETERS
+Module parameters
 -----------------
 
-Panic on UE control file:
-
-	'edac_mc_panic_on_ue'
+- ``edac_mc_panic_on_ue`` - Panic on UE control file
 
 	An uncorrectable error will cause a machine panic.  This is usually
 	desirable.  It is a bad idea to continue when an uncorrectable error
@@ -557,40 +550,49 @@ Panic on UE control file:
 	corruption. If the kernel has MCE configured, then EDAC will never
 	notice the UE.
 
-	LOAD TIME: module/kernel parameter: edac_mc_panic_on_ue=[0|1]
+	LOAD TIME::
+
+		module/kernel parameter: edac_mc_panic_on_ue=[0|1]
+
+	RUN TIME::
 
-	RUN TIME:  echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
+		echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
 
 
-Log UE control file:
+- ``edac_mc_log_ue`` - Log UE control file
 
-	'edac_mc_log_ue'
 
 	Generate kernel messages describing uncorrectable errors.  These errors
 	are reported through the system message log system.  UE statistics
 	will be accumulated even when UE logging is disabled.
 
-	LOAD TIME: module/kernel parameter: edac_mc_log_ue=[0|1]
+	LOAD TIME::
 
-	RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
+		module/kernel parameter: edac_mc_log_ue=[0|1]
 
+	RUN TIME::
 
-Log CE control file:
+		echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
+
+
+- ``edac_mc_log_ce`` - Log CE control file
 
-	'edac_mc_log_ce'
 
 	Generate kernel messages describing correctable errors.  These
 	errors are reported through the system message log system.
 	CE statistics will be accumulated even when CE logging is disabled.
 
-	LOAD TIME: module/kernel parameter: edac_mc_log_ce=[0|1]
+	LOAD TIME::
+
+		module/kernel parameter: edac_mc_log_ce=[0|1]
+
+	RUN TIME::
 
-	RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
+		echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
 
 
-Polling period control file:
+- ``edac_mc_poll_msec`` - Polling period control file
 
-	'edac_mc_poll_msec'
 
 	The time period, in milliseconds, for polling for error information.
 	Too small a value wastes resources.  Too large a value might delay
@@ -599,27 +601,33 @@ Polling period control file:
 	default. Systems which require all the bandwidth they can get, may
 	increase this.
 
-	LOAD TIME: module/kernel parameter: edac_mc_poll_msec=[0|1]
+	LOAD TIME::
 
-	RUN TIME: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
+		module/kernel parameter: edac_mc_poll_msec=[0|1]
 
+	RUN TIME::
 
-Panic on PCI PARITY Error:
+		echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
 
-	'panic_on_pci_parity'
+
+- ``panic_on_pci_parity`` - Panic on PCI PARITY Error
 
 
 	This control file enables or disables panicking when a parity
 	error has been detected.
 
 
-	module/kernel parameter: edac_panic_on_pci_pe=[0|1]
+	module/kernel parameter::
+
+			edac_panic_on_pci_pe=[0|1]
+
+	Enable::
+
+		echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
 
-	Enable:
-	echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
+	Disable::
 
-	Disable:
-	echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
+		echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
 
 
 
@@ -631,28 +639,31 @@ and APIs for the EDAC_DEVICE.
 
 User space access to an edac_device is through the sysfs interface.
 
-At the location /sys/devices/system/edac (sysfs) new edac_device devices will
-appear.
+At the location ``/sys/devices/system/edac`` (sysfs) new edac_device devices
+will appear.
 
-There is a three level tree beneath the above 'edac' directory. For example,
-the 'test_device_edac' device (found at the bluesmoke.sourceforget.net website)
-installs itself as:
+There is a three level tree beneath the above ``edac`` directory. For example,
+the ``test_device_edac`` device (found at the http://bluesmoke.sourceforget.net
+website) installs itself as::
 
-	/sys/devices/systm/edac/test-instance
+	/sys/devices/system/edac/test-instance
 
-in this directory are various controls, a symlink and one or more 'instance'
+in this directory are various controls, a symlink and one or more ``instance``
 directories.
 
 The standard default controls are:
 
+	==============	=======================================================
 	log_ce		boolean to log CE events
 	log_ue		boolean to log UE events
-	panic_on_ue	boolean to 'panic' the system if an UE is encountered
+	panic_on_ue	boolean to ``panic`` the system if an UE is encountered
 			(default off, can be set true via startup script)
 	poll_msec	time period between POLL cycles for events
+	==============	=======================================================
 
 The test_device_edac device adds at least one of its own custom control:
 
+	==============	==================================================
 	test_bits	which in the current test driver does nothing but
 			show how it is installed. A ported driver can
 			add one or more such controls and/or attributes
@@ -660,42 +671,52 @@ The test_device_edac device adds at least one of its own custom control:
 			One out-of-tree driver uses controls here to allow
 			for ERROR INJECTION operations to hardware
 			injection registers
+	==============	==================================================
 
 The symlink points to the 'struct dev' that is registered for this edac_device.
 
-INSTANCES
+Instances
 ---------
 
-One or more instance directories are present. For the 'test_device_edac' case:
+One or more instance directories are present. For the ``test_device_edac``
+case:
 
-	test-instance0
+	+----------------+
+	| test-instance0 |
+	+----------------+
 
 
 In this directory there are two default counter attributes, which are totals of
 counter in deeper subdirectories.
 
+	==============	====================================
 	ce_count	total of CE events of subdirectories
 	ue_count	total of UE events of subdirectories
+	==============	====================================
 
-BLOCKS
+Blocks
 ------
 
-At the lowest directory level is the 'block' directory. There can be 0, 1
-or more blocks specified in each instance.
-
-	test-block0
+At the lowest directory level is the ``block`` directory. There can be 0, 1
+or more blocks specified in each instance:
 
+	+-------------+
+	| test-block0 |
+	+-------------+
 
 In this directory the default attributes are:
 
-	ce_count	which is counter of CE events for this 'block'
+	==============	================================================
+	ce_count	which is counter of CE events for this ``block``
 			of hardware being monitored
-	ue_count	which is counter of UE events for this 'block'
+	ue_count	which is counter of UE events for this ``block``
 			of hardware being monitored
+	==============	================================================
 
 
-The 'test_device_edac' device adds 4 attributes and 1 control:
+The ``test_device_edac`` device adds 4 attributes and 1 control:
 
+	================== ====================================================
 	test-block-bits-0	for every POLL cycle this counter
 				is incremented
 	test-block-bits-1	every 10 cycles, this counter is bumped once,
@@ -704,20 +725,23 @@ The 'test_device_edac' device adds 4 attributes and 1 control:
 				and test-block-bits-1 is set to 0
 	test-block-bits-3	every 1000 cycles, this counter is bumped once,
 				and test-block-bits-2 is set to 0
+	================== ====================================================
 
 
+	================== ====================================================
 	reset-counters		writing ANY thing to this control will
 				reset all the above counters.
+	================== ====================================================
 
 
-Use of the 'test_device_edac' driver should enable any others to create their own
+Use of the ``test_device_edac`` driver should enable any others to create their own
 unique drivers for their hardware systems.
 
-The 'test_device_edac' sample driver is located at the
-bluesmoke.sourceforge.net project site for EDAC.
+The ``test_device_edac`` sample driver is located at the
+http://bluesmoke.sourceforge.net project site for EDAC.
 
 
-NEHALEM USAGE OF EDAC APIs
+Nehalem Usage of EDAC APIs
 --------------------------
 
 This chapter documents some EXPERIMENTAL mappings for EDAC API to handle
@@ -739,7 +763,8 @@ were done at i7core_edac driver. This chapter will cover those differences
    As EDAC API maps the minimum unity is csrows, the driver sequentially
    maps channel/dimm into different csrows.
 
-   For example, supposing the following layout:
+   For example, supposing the following layout::
+
 	Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
 	  dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
 	  dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
@@ -747,14 +772,15 @@ were done at i7core_edac driver. This chapter will cover those differences
 	  dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
 	Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
 	  dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
-   The driver will map it as:
+
+   The driver will map it as::
+
 	csrow0: channel 0, dimm0
 	csrow1: channel 0, dimm1
 	csrow2: channel 1, dimm0
 	csrow3: channel 2, dimm0
 
-exports one
-   DIMM per csrow.
+   exports one DIMM per csrow.
 
    Each QPI is exported as a different memory controller.
 
@@ -762,47 +788,53 @@ exports one
    functionality via some error injection nodes:
 
    For injecting a memory error, there are some sysfs nodes, under
-   /sys/devices/system/edac/mc/mc?/:
+   ``/sys/devices/system/edac/mc/mc?/``:
 
-   inject_addrmatch/*:
+   - ``inject_addrmatch/*``:
       Controls the error injection mask register. It is possible to specify
-      several characteristics of the address to match an error code:
+      several characteristics of the address to match an error code::
+
          dimm = the affected dimm. Numbers are relative to a channel;
          rank = the memory rank;
          channel = the channel that will generate an error;
          bank = the affected bank;
          page = the page address;
          column (or col) = the address column.
+
       each of the above values can be set to "any" to match any valid value.
 
       At driver init, all values are set to any.
 
       For example, to generate an error at rank 1 of dimm 2, for any channel,
-      any bank, any page, any column:
+      any bank, any page, any column::
+
 		echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
 		echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
 
-	To return to the default behaviour of matching any, you can do:
+	To return to the default behaviour of matching any, you can do::
+
 		echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
 		echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
 
-   inject_eccmask:
-       specifies what bits will have troubles,
+   - ``inject_eccmask``:
+          specifies what bits will have troubles,
+
+   - ``inject_section``:
+       specifies what ECC cache section will get the error::
 
-   inject_section:
-       specifies what ECC cache section will get the error:
 		3 for both
 		2 for the highest
 		1 for the lowest
 
-   inject_type:
-       specifies the type of error, being a combination of the following bits:
+   - ``inject_type``:
+       specifies the type of error, being a combination of the following bits::
+
 		bit 0 - repeat
 		bit 1 - ecc
 		bit 2 - parity
 
-       inject_enable starts the error generation when something different
-       than 0 is written.
+   - ``inject_enable``:
+       starts the error generation when something different than 0 is written.
 
    All inject vars can be read. root permission is needed for write.
 
@@ -811,21 +843,21 @@ exports one
    also produce an error.
 
    For example, the following code will generate an error for any write access
-   at socket 0, on any DIMM/address on channel 2:
+   at socket 0, on any DIMM/address on channel 2::
 
-   echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
-   echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
-   echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
-   echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
-   echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
-   dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null
+	echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
+	echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
+	echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
+	echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
+	echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
+	dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null
 
    For socket 1, it is needed to replace "mc0" by "mc1" at the above
    commands.
 
-   The generated error message will look like:
+   The generated error message will look like::
 
-   EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))
+	EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))
 
 3) Nehalem specific Corrected Error memory counters
 
@@ -837,9 +869,9 @@ exports one
    granularity than the default ones), the driver exposes those registers for
    UDIMM memories.
 
-   They can be read by looking at the contents of all_channel_counts/
+   They can be read by looking at the contents of ``all_channel_counts/``::
 
-   $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
+     $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
 	/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
 	0
 	/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
@@ -849,17 +881,21 @@ exports one
 
    What happens here is that errors on different csrows, but at the same
    dimm number will increment the same counter.
-   So, in this memory mapping:
+   So, in this memory mapping::
+
 	csrow0: channel 0, dimm0
 	csrow1: channel 0, dimm1
 	csrow2: channel 1, dimm0
 	csrow3: channel 2, dimm0
+
    The hardware will increment udimm0 for an error at the first dimm at either
-	csrow0, csrow2  or csrow3;
+   csrow0, csrow2  or csrow3;
+
    The hardware will increment udimm1 for an error at the second dimm at either
-	csrow0, csrow2  or csrow3;
+   csrow0, csrow2  or csrow3;
+
    The hardware will increment udimm2 for an error at the third dimm at either
-	csrow0, csrow2  or csrow3;
+   csrow0, csrow2  or csrow3;
 
 4) Standard error counters
 
@@ -868,65 +904,68 @@ exports one
    possible that some errors could be lost. With rdimm's, they display the
    contents of the registers
 
-AMD64_EDAC REFERENCE DOCUMENTS USED
------------------------------------
-amd64_edac module is based on the following documents
+Reference documents used on ``amd64_edac``
+------------------------------------------
+
+``amd64_edac`` module is based on the following documents
 (available from http://support.amd.com/en-us/search/tech-docs):
 
-1. Title:  BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
+1. :Title:  BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
 	   Opteron Processors
-   AMD publication #: 26094
-   Revision: 3.26
-   Link: http://support.amd.com/TechDocs/26094.PDF
+   :AMD publication #: 26094
+   :Revision: 3.26
+   :Link: http://support.amd.com/TechDocs/26094.PDF
 
-2. Title:  BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
+2. :Title:  BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
 	   Processors
-   AMD publication #: 32559
-   Revision: 3.00
-   Issue Date: May 2006
-   Link: http://support.amd.com/TechDocs/32559.pdf
+   :AMD publication #: 32559
+   :Revision: 3.00
+   :Issue Date: May 2006
+   :Link: http://support.amd.com/TechDocs/32559.pdf
 
-3. Title:  BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
+3. :Title:  BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
 	   Processors
-   AMD publication #: 31116
-   Revision: 3.00
-   Issue Date: September 07, 2007
-   Link: http://support.amd.com/TechDocs/31116.pdf
+   :AMD publication #: 31116
+   :Revision: 3.00
+   :Issue Date: September 07, 2007
+   :Link: http://support.amd.com/TechDocs/31116.pdf
 
-4. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
+4. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
 	  Models 30h-3Fh Processors
-   AMD publication #: 49125
-   Revision: 3.06
-   Issue Date: 2/12/2015 (latest release)
-   Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
+   :AMD publication #: 49125
+   :Revision: 3.06
+   :Issue Date: 2/12/2015 (latest release)
+   :Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
 
-5. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
+5. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
 	  Models 60h-6Fh Processors
-   AMD publication #: 50742
-   Revision: 3.01
-   Issue Date: 7/23/2015 (latest release)
-   Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
+   :AMD publication #: 50742
+   :Revision: 3.01
+   :Issue Date: 7/23/2015 (latest release)
+   :Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
 
-6. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h
+6. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h
 	  Models 00h-0Fh Processors
-   AMD publication #: 48751
-   Revision: 3.03
-   Issue Date: 2/23/2015 (latest release)
-   Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
+   :AMD publication #: 48751
+   :Revision: 3.03
+   :Issue Date: 2/23/2015 (latest release)
+   :Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
+
+Credits
+=======
+
+* Written by Doug Thompson <dougthompson@xmission.com>
 
-CREDITS:
-========
+  - 7 Dec 2005
+  - 17 Jul 2007	Updated
 
-Written by Doug Thompson <dougthompson@xmission.com>
-7 Dec 2005
-17 Jul 2007	Updated
+* |copy| Mauro Carvalho Chehab
 
-(c) Mauro Carvalho Chehab
-05 Aug 2009	Nehalem interface
+  - 05 Aug 2009	Nehalem interface
 
-EDAC authors/maintainers:
+* EDAC authors/maintainers:
 
-	Doug Thompson, Dave Jiang, Dave Peterson et al,
-	Mauro Carvalho Chehab
-	Borislav Petkov
-	original author: Thayne Harbaugh
+  - Doug Thompson, Dave Jiang, Dave Peterson et al,
+  - Mauro Carvalho Chehab
+  - Borislav Petkov
+  - original author: Thayne Harbaugh