diff options
| author | Florian Fainelli <f.fainelli@gmail.com> | 2019-04-07 14:40:50 -0700 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2020-01-05 13:44:04 -0800 |
| commit | add427c49e92c78519d0ff1728ea66d9e52f1fc9 (patch) | |
| tree | f2644e631ec0582ed134c39b928736d91e44bebc | |
| parent | ea1e84d1bd3c0845f814f06d08005bb9cd6da700 (diff) | |
soc: bcm: brcmstb: biuctrl: Update programming for 7211
Add a matching entry for 7211 which can be programmed with the same
BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the
function to include a72 in the name to reflect this applies to both
types of 64-bit capable CPUs that we support (Brahma-B53 and
Cortex-A72).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| -rw-r--r-- | drivers/soc/bcm/brcmstb/biuctrl.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index d766577bc5d4..61731e01f94b 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -107,7 +107,8 @@ static int __init mcp_write_pairing_set(void) return 0; } -static const u32 b53_mach_compat[] = { +static const u32 a72_b53_mach_compat[] = { + 0x7211, 0x7216, 0x7255, 0x7260, @@ -116,19 +117,19 @@ static const u32 b53_mach_compat[] = { 0x7278, }; -static void __init mcp_b53_set(void) +static void __init mcp_a72_b53_set(void) { unsigned int i; u32 reg; reg = brcmstb_get_family_id(); - for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) { - if (BRCM_ID(reg) == b53_mach_compat[i]) + for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) { + if (BRCM_ID(reg) == a72_b53_mach_compat[i]) break; } - if (i == ARRAY_SIZE(b53_mach_compat)) + if (i == ARRAY_SIZE(a72_b53_mach_compat)) return; /* Set all 3 MCP interfaces to 8 credits */ @@ -261,7 +262,7 @@ static int __init brcmstb_biuctrl_init(void) return ret; } - mcp_b53_set(); + mcp_a72_b53_set(); #ifdef CONFIG_PM_SLEEP register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); #endif |