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authorTao Zhou <tao.zhou1@amd.com>2020-10-02 11:21:47 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-10-12 14:00:01 -0400
commita2468e043ae48fbeabdc966847a6675da47a7dc4 (patch)
treedc3b2895b84c4e7da1e803e8e5d3becf19d93719
parentcd294f9a645f254bb4f5e15c64eb8aec5d4a4fda (diff)
drm/amdgpu: add dimgrey_cavefish asic type
Add chip type for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c1
-rw-r--r--include/drm/amd_asic_type.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 576cf3752009..0539ea726d8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -117,6 +117,7 @@ const char *amdgpu_asic_name[] = {
"SIENNA_CICHLID",
"NAVY_FLOUNDER",
"VANGOGH",
+ "DIMGREY_CAVEFISH",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 6d01cf04b77f..cde3c8c9f20c 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -57,6 +57,7 @@ enum amd_asic_type {
CHIP_SIENNA_CICHLID, /* 28 */
CHIP_NAVY_FLOUNDER, /* 29 */
CHIP_VANGOGH, /* 30 */
+ CHIP_DIMGREY_CAVEFISH, /* 31 */
CHIP_LAST,
};