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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-10-31 18:12:48 -0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 23:51:25 +0100
commit9a76b1c68ffb843ad6f31b746141365fdf262b97 (patch)
tree36c37bfe29cf95615f4db6813a2db0ef980c9912
parent69d3ed5a6fc2e7ac8f848711d9bb6af9b3baf77b (diff)
drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder
... instead of PIPECONF_INTERLACE_MASK. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: applied the change by hand due to patch reorder.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7bab7adf7345..787e62a44542 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1732,7 +1732,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
val = TRANS_ENABLE;
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+ if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+ PIPECONF_INTERLACED_ILK)
val |= TRANS_INTERLACED;
else
val |= TRANS_PROGRESSIVE;