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authorSiddha, Suresh B <suresh.b.siddha@intel.com>2006-12-07 02:14:10 +0100
committerAndi Kleen <andi@basil.nowhere.org>2006-12-07 02:14:10 +0100
commit9899f826fc90beba4f78083f6230e06cbe1050c9 (patch)
tree5d493eaa17da85c57746ffcc2e01a8a6f484fa5f
parent72486f1f8f0a2bc828b9d30cf4690cf2dd6807fc (diff)
[PATCH] x86-64: add genapic_force
Add genapic_force. Used by the next Intel quirks patch. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Andi Kleen <ak@suse.de> Cc: "Li, Shaohua" <shaohua.li@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org>
-rw-r--r--arch/x86_64/kernel/genapic.c9
-rw-r--r--include/asm-x86_64/genapic.h2
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/x86_64/kernel/genapic.c b/arch/x86_64/kernel/genapic.c
index 8e78a75d1866..b007433f96bb 100644
--- a/arch/x86_64/kernel/genapic.c
+++ b/arch/x86_64/kernel/genapic.c
@@ -33,7 +33,7 @@ extern struct genapic apic_flat;
extern struct genapic apic_physflat;
struct genapic *genapic = &apic_flat;
-
+struct genapic *genapic_force;
/*
* Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
@@ -46,6 +46,13 @@ void __init clustered_apic_check(void)
u8 cluster_cnt[NUM_APIC_CLUSTERS];
int max_apic = 0;
+ /* genapic selection can be forced because of certain quirks.
+ */
+ if (genapic_force) {
+ genapic = genapic_force;
+ goto print;
+ }
+
#if defined(CONFIG_ACPI)
/*
* Some x86_64 machines use physical APIC mode regardless of how many
diff --git a/include/asm-x86_64/genapic.h b/include/asm-x86_64/genapic.h
index a0e9a4b93484..b80f4bb5f273 100644
--- a/include/asm-x86_64/genapic.h
+++ b/include/asm-x86_64/genapic.h
@@ -30,6 +30,6 @@ struct genapic {
};
-extern struct genapic *genapic;
+extern struct genapic *genapic, *genapic_force, apic_flat;
#endif