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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2015-09-14 11:55:41 +0300
committerVinod Koul <vinod.koul@intel.com>2015-09-25 07:54:05 +0530
commit97c37accd38f6136fa0abbdef01b5f864e91e6c7 (patch)
treebff92ff0e32a0afbeeabdd01633b40c81982c66c
parent2e9b55becc905207eb01e24bc282f8062cc497b5 (diff)
dmaengine: idma64: use lo_hi_readq() / lo_hi_writeq()
There are already helper functions to do 64-bit I/O on 32-bit machines, thus we don't need to reinvent the wheel. In our case we can't use readq() / writeq() even on 64-bit kernel since there is a hardware limitation (OCP bus is a 32-bit bus). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/idma64.h12
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
index 323c3f13ba2f..f6aeff0af8a5 100644
--- a/drivers/dma/idma64.h
+++ b/drivers/dma/idma64.h
@@ -16,6 +16,8 @@
#include <linux/spinlock.h>
#include <linux/types.h>
+#include <asm-generic/io-64-nonatomic-lo-hi.h>
+
#include "virt-dma.h"
/* Channel registers */
@@ -166,19 +168,13 @@ static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
{
- u64 l, h;
-
- l = idma64c_readl(idma64c, offset);
- h = idma64c_readl(idma64c, offset + 4);
-
- return l | (h << 32);
+ return lo_hi_readq(idma64c->regs + offset);
}
static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
u64 value)
{
- idma64c_writel(idma64c, offset, value);
- idma64c_writel(idma64c, offset + 4, value >> 32);
+ lo_hi_writeq(value, idma64c->regs + offset);
}
#define channel_readq(idma64c, reg) \