diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-10-29 20:54:03 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-20 11:18:20 -0800 |
| commit | 96cb6933403ce9136b49b002ceb8da82037f4fe4 (patch) | |
| tree | 38d95eb6622e9c80f6231e66bf42952d639749e4 | |
| parent | 3fe003f944755f6d959387f9568d271512dcb12d (diff) | |
clk: shmobile: rcar-gen2: Spelling/Grammar: dependant of, ouput
s/dependant of/dependent on/
s/ouput/output/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/shmobile/clk-rcar-gen2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c index 745496f7ee9c..841977240305 100644 --- a/drivers/clk/shmobile/clk-rcar-gen2.c +++ b/drivers/clk/shmobile/clk-rcar-gen2.c @@ -115,7 +115,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, * * Using experimental measurements, it seems that no more than * ~10 iterations are needed, independently of the CPU rate. - * Since this value might be dependant of external xtal rate, pll1 + * Since this value might be dependent on external xtal rate, pll1 * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ @@ -262,7 +262,7 @@ static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) * 1 1 0 30 / 2 x172/2 x208/2 x106 * 1 1 1 30 / 2 x172/2 x208/2 x88 * - * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) + * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2) */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ |