diff options
| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-10-30 13:56:26 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-11-01 12:23:17 +0200 |
| commit | 808517e2c3786508150ffe965a9e219e5915204f (patch) | |
| tree | 030355dd0d865727bf15bfd2c165cbd7dc097674 | |
| parent | 03ad7d8821ec44513d514a5e6b17b60e732e1182 (diff) | |
drm/i915/icl: Add DSI packet payload/header registers
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/18275c49215e512347a14bc38715314c2d6f95a4.1540900289.git.jani.nikula@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6f2e6233f4f5..af6bf8301d33 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10527,6 +10527,28 @@ enum skl_power_gate { #define MAX_HEADER_CREDIT 0x10 #define MAX_PLOAD_CREDIT 0x40 +#define _DSI_CMD_TXHDR_0 0x6b100 +#define _DSI_CMD_TXHDR_1 0x6b900 +#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ + _DSI_CMD_TXHDR_0,\ + _DSI_CMD_TXHDR_1) +#define PAYLOAD_PRESENT (1 << 31) +#define LP_DATA_TRANSFER (1 << 30) +#define VBLANK_FENCE (1 << 29) +#define PARAM_WC_MASK (0xffff << 8) +#define PARAM_WC_LOWER_SHIFT 8 +#define PARAM_WC_UPPER_SHIFT 16 +#define VC_MASK (0x3 << 6) +#define VC_SHIFT 6 +#define DT_MASK (0x3f << 0) +#define DT_SHIFT 0 + +#define _DSI_CMD_TXPYLD_0 0x6b104 +#define _DSI_CMD_TXPYLD_1 0x6b904 +#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ + _DSI_CMD_TXPYLD_0,\ + _DSI_CMD_TXPYLD_1) + #define _DSI_LP_MSG_0 0x6b0d8 #define _DSI_LP_MSG_1 0x6b8d8 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ |