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authorHeiner Kallweit <hkallweit1@gmail.com>2018-09-19 22:02:11 +0200
committerDavid S. Miller <davem@davemloft.net>2018-09-19 23:06:30 -0700
commit806a81fcf6880c8592fae62cac82e850f37301b8 (patch)
treecab3dc19db183c4c23850fe3461efddc790cf45a
parent7a67e11d901e17c3222d226c345be555106faae6 (diff)
r8169: remove duplicated RTL8169s PHY initialization steps
Setting register 0x82 to value 01 is done a few lines before for all chip versions <= 06 anyway. And setting PHY register 0x0b to value 00 is done at the end of rtl8169s_hw_phy_config() already. So we can remove this. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/realtek/r8169.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 1b49d9e783f8..1843fafb62d1 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -4055,15 +4055,6 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
RTL_W8(tp, 0x82, 0x01);
}
- if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
- netif_dbg(tp, drv, dev,
- "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
- RTL_W8(tp, 0x82, 0x01);
- netif_dbg(tp, drv, dev,
- "Set PHY Reg 0x0bh = 0x00h\n");
- rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
- }
-
/* We may have called phy_speed_down before */
phy_speed_up(dev->phydev);