diff options
| author | Mark Zhang <markz@nvidia.com> | 2012-10-16 16:31:49 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-10-16 11:14:34 -0600 |
| commit | 786621308cfbb9421a54773e57dbdbe504c417cc (patch) | |
| tree | 19ae13afa378872be16f842edcdb4761f1159d8b | |
| parent | ddffeb8c4d0331609ef2581d84de4d763607bd37 (diff) | |
ARM: tegra30: clk: Fix output_rate overflow
Change the type of variable from "unsigned long" to "u64".
This avoids the overflow while clock rate calculating.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra30_clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 5cd502c27163..e9de5dfd94ec 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, { struct clk_tegra *c = to_clk_tegra(hw); unsigned long input_rate = *prate; - unsigned long output_rate = *prate; + u64 output_rate = *prate; const struct clk_pll_freq_table *sel; struct clk_pll_freq_table cfg; int mul; |