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| author | Yash Shah <yash.shah@sifive.com> | 2020-12-08 10:25:33 +0530 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-01-07 17:37:24 -0800 |
| commit | 75e6d7248efccc2b13d0f3811b29d3e5cb04bcad (patch) | |
| tree | de17be73d6d80596bbbfa95cd693d4f77aaf513c | |
| parent | 507308b8ccc90d37b07bfca8ffe130435d6b354f (diff) | |
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6925e0b16e4..eb6843f69f7c 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,11 +28,17 @@ properties: - items: - enum: - sifive,rocket0 + - sifive,bullet0 - sifive,e5 + - sifive,e7 - sifive,e51 + - sifive,e71 - sifive,u54-mc + - sifive,u74-mc - sifive,u54 + - sifive,u74 - sifive,u5 + - sifive,u7 - const: riscv - const: riscv # Simulator only description: |