diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-06 13:29:59 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-11 20:26:17 -0500 |
| commit | 74e69079e2e81f656ef6a17e98f5b597b9b3f9bd (patch) | |
| tree | 5737dae0a8739eb2925dad92f476eeba8a36a788 | |
| parent | afb374f8ac0715ff10e580e8d83c206dc4b7017e (diff) | |
PCI: armada: Remove redundant struct armada8k_pcie.base
The struct armada8k_pcie.base pointer is always a constant offset from
struct pcie_port.dbi_base. Encode that offset in the register macros so we
don't need to maintain the armada8k_pcie.base pointer. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
| -rw-r--r-- | drivers/pci/host/pcie-armada8k.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/drivers/pci/host/pcie-armada8k.c b/drivers/pci/host/pcie-armada8k.c index 121f6c8f4d2e..cfa50f592d2d 100644 --- a/drivers/pci/host/pcie-armada8k.c +++ b/drivers/pci/host/pcie-armada8k.c @@ -29,34 +29,33 @@ #include "pcie-designware.h" struct armada8k_pcie { - void __iomem *base; struct clk *clk; struct pcie_port pp; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000 -#define PCIE_GLOBAL_CONTROL_REG 0x0 +#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) #define PCIE_APP_LTSSM_EN BIT(2) #define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ -#define PCIE_GLOBAL_STATUS_REG 0x8 +#define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8) #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) -#define PCIE_GLOBAL_INT_CAUSE1_REG 0x1C -#define PCIE_GLOBAL_INT_MASK1_REG 0x20 +#define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) +#define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) #define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_B_ASSERT_MASK BIT(10) #define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_D_ASSERT_MASK BIT(12) -#define PCIE_ARCACHE_TRC_REG 0x50 -#define PCIE_AWCACHE_TRC_REG 0x54 -#define PCIE_ARUSER_REG 0x5C -#define PCIE_AWUSER_REG 0x60 +#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) +#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) +#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) +#define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60) /* * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write * allocate @@ -73,7 +72,7 @@ struct armada8k_pcie { static int armada8k_pcie_link_up(struct pcie_port *pp) { struct armada8k_pcie *pcie = to_armada8k_pcie(pp); - void __iomem *base = pcie->base; + void __iomem *base = pcie->pp.dbi_base; u32 reg; u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; @@ -89,7 +88,7 @@ static int armada8k_pcie_link_up(struct pcie_port *pp) static void armada8k_pcie_establish_link(struct pcie_port *pp) { struct armada8k_pcie *pcie = to_armada8k_pcie(pp); - void __iomem *base = pcie->base; + void __iomem *base = pcie->pp.dbi_base; u32 reg; if (!dw_pcie_link_up(pp)) { @@ -148,7 +147,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) { struct pcie_port *pp = arg; struct armada8k_pcie *pcie = to_armada8k_pcie(pp); - void __iomem *base = pcie->base; + void __iomem *base = pcie->pp.dbi_base; u32 val; /* @@ -228,8 +227,6 @@ static int armada8k_pcie_probe(struct platform_device *pdev) goto fail; } - pcie->base = pp->dbi_base + PCIE_VENDOR_REGS_OFFSET; - ret = armada8k_add_pcie_port(pp, pdev); if (ret) goto fail; |