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authorLEROY Christophe <christophe.leroy@c-s.fr>2013-09-24 10:18:39 +0200
committerScott Wood <scottwood@freescale.com>2013-10-28 21:11:21 -0500
commit4e591f3c0a618b8230a37bfff64b59e76374f2e5 (patch)
treea9d1c008e9fe324f95a03e464961a855de388026
parent9e0967572e5a0e8c887b2d71192bdad342e8a3dd (diff)
powerpc/8xx: Fixing issue with CONFIG_PIN_TLB
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was missing before the pinning of the third 8Mb page. As the index is decremented module 28 (MD_RSV4D is set) after every DTLB update, the third 8Mbytes page was not pinned. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
-rw-r--r--arch/powerpc/kernel/head_8xx.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1b92a97b1b04..7ee876d2adb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -858,6 +858,9 @@ initial_mmu:
addis r11, r11, 0x0080 /* Add 8M */
mtspr SPRN_MD_RPN, r11
+ addi r10, r10, 0x0100
+ mtspr SPRN_MD_CTR, r10
+
addis r8, r8, 0x0080 /* Add 8M */
mtspr SPRN_MD_EPN, r8
mtspr SPRN_MD_TWC, r9