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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-06-27 14:52:42 +0200
committerStephen Boyd <sboyd@kernel.org>2019-10-03 14:00:20 -0700
commit4d8fb4948472c976d0c6dcf3380f92332dd660c1 (patch)
treed06593bfe388c37f793d0b36f8e2680729046702
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff)
clk: mvebu: armada-37xx-periph: add PCIe gated clock
The PCIe clock is a gated clock which has the same source as GbE0 (both IPs share a set of registers). This source clock is called 'gbe_core' in the driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 5fc6d486a381..d9d84299da46 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -303,6 +303,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
+static PERIPH_GATE(pcie, 14);
static struct clk_periph_data data_sb[] = {
REF_CLK_MUX_DD(gbe_50),
@@ -318,6 +319,7 @@ static struct clk_periph_data data_sb[] = {
REF_CLK_FULL_DD(sdio),
REF_CLK_FULL_DD(usb32_usb2_sys),
REF_CLK_FULL_DD(usb32_ss_sys),
+ REF_CLK_GATE(pcie, "gbe_core"),
{ },
};