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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2010-03-06 13:47:07 +0100
committerIngo Molnar <mingo@elte.hu>2010-03-10 13:23:36 +0100
commit4807e3d5dc7bb7057dd6ca3abb09f3da2eb8c323 (patch)
tree408ad33e37e9c0c75e3d8084e6f995d3ba91c342
parent8f4aebd2be9892bf8fb79a2d8576d3f3ee7f00f6 (diff)
perf, x86: Fix PEBS enable/disable vs cpuc->enabled
We should never call ->enable with the pmu enabled, and we _can_ have ->disable called with the pmu enabled. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arnaldo Carvalho de Melo <acme@infradead.org> Cc: paulus@samba.org Cc: eranian@google.com Cc: robert.richter@amd.com Cc: fweisbec@gmail.com LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_ds.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 66c6962f15f9..9ad0e67b9c82 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -338,7 +338,7 @@ static void intel_pmu_pebs_enable(struct perf_event *event)
hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
val |= 1ULL << hwc->idx;
- wrmsrl(MSR_IA32_PEBS_ENABLE, val);
+ WARN_ON_ONCE(cpuc->enabled);
if (x86_pmu.intel_cap.pebs_trap)
intel_pmu_lbr_enable(event);
@@ -351,7 +351,8 @@ static void intel_pmu_pebs_disable(struct perf_event *event)
u64 val = cpuc->pebs_enabled;
val &= ~(1ULL << hwc->idx);
- wrmsrl(MSR_IA32_PEBS_ENABLE, val);
+ if (cpuc->enabled)
+ wrmsrl(MSR_IA32_PEBS_ENABLE, val);
hwc->config |= ARCH_PERFMON_EVENTSEL_INT;