diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2019-12-20 15:03:03 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-12-23 14:59:57 -0500 |
| commit | 468288863e94cf7115317005bc34752c79a4bc74 (patch) | |
| tree | b7cc6da479fae112580d64ba9f039fb847185c3b | |
| parent | d24d26540bab53e093ec5e290071883e0f1d152c (diff) | |
drm/amdgpu/smu: add peak profile support for navi12
Add defined peak sclk for navi12 peak profile mode.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c33744a0d46b..106434689ec5 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1628,6 +1628,9 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) break; } break; + case CHIP_NAVI12: + sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; + break; default: ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level); if (ret) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h index ec03c7992f6d..f109401c2ee8 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h @@ -33,6 +33,8 @@ #define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717) #define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448) +#define NAVI12_UMD_PSTATE_PEAK_GFXCLK (1100) + #define NAVI10_VOLTAGE_SCALE (4) #define smnPCIE_LC_SPEED_CNTL 0x11140290 |