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authorDouglas Anderson <dianders@chromium.org>2019-06-20 11:20:56 -0700
committerHeiko Stuebner <heiko@sntech.de>2019-08-16 13:27:05 +0200
commit3c29ba8e7c78dee1a8a59cadf235d6b93489a3b4 (patch)
tree003f2610c94f9ec3c7c6f46013cd8f44f2913500
parent6f79fcc6c9e311d489989e0909d86c0762d3ac61 (diff)
Revert "ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators"
This reverts commit 1f45e8c6d0161f044d679f242fe7514e2625af4a. This 100 ms mystery delay is not on downstream kernels and no longer seems needed on upstream kernels either [1]. Presumably something in the meantime has made things better. A few possibilities for patches that have landed in the meantime that could have made this better are commit 3157694d8c7f ("pwm-backlight: Add support for PWM delays proprieties."), commit 5fb5caee92ba ("pwm-backlight: Enable/disable the PWM before/after LCD enable toggle."), and commit 6d5922dd0d60 ("ARM: dts: rockchip: set PWM delay backlight settings for Veyron") Let's revert and get our 100 ms back. [1] https://lkml.kernel.org/r/2226970.BAPq4liE1j@diego Signed-off-by: Douglas Anderson <dianders@chromium.org> [rebased on top of the recent veyron display cleanup] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-edp.dtsi1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
index d74b6205b022..b12e061c5f7f 100644
--- a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
@@ -24,7 +24,6 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
- startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};