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authorVladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>2017-07-09 20:40:05 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-07-17 11:51:00 -0700
commit3a11c6618e176aecf129c6d2f0cbc9440672f378 (patch)
tree7714295489241cfd13ddb0ba856ab2be9e83c79f
parentb191155541f2a4cfbe62697c8d65919549f948c0 (diff)
dt: Add bindings for IDT VersaClock 5P49V5925
IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers. Input clock source can be taken only from external reference clock. Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--Documentation/devicetree/bindings/clock/idt,versaclock5.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 66ef0a009b95..05a245c9df08 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -8,6 +8,7 @@ generators providing from 3 to 12 output clocks.
Required properties:
- compatible: shall be one of
"idt,5p49v5923"
+ "idt,5p49v5925"
"idt,5p49v5933"
"idt,5p49v5935"
"idt,5p49v6901"
@@ -15,6 +16,7 @@ Required properties:
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- 5p49v5923 and
+ 5p49v5925 and
5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
@@ -23,6 +25,7 @@ Required properties:
clock.
- clock-names: from common clock binding; clock input names, can be
- 5p49v5923 and
+ 5p49v5925 and
5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
@@ -42,6 +45,7 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
+5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1