diff options
| author | Antoine Ténart <antoine.tenart@free-electrons.com> | 2017-06-15 09:56:19 +0200 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2017-06-20 11:21:43 +0800 |
| commit | 39ba1bb4a4624bc0215531e0d5fdbbf0325c0c0e (patch) | |
| tree | 4d398e78d27c40bf0469642332c4e6446ee575f6 | |
| parent | aefa794efed40cc6f8225646d75deda879b98256 (diff) | |
crypto: inside-secure - fix incorrect DSE data cache setting
Set the correct value to the DSE data cache, using WR_CACHE_3BITS
instead of RD_CACHE_3BITS. This fixes an incorrect setting and helps
improving performances.
Reported-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| -rw-r--r-- | drivers/crypto/inside-secure/safexcel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/inside-secure/safexcel.c b/drivers/crypto/inside-secure/safexcel.c index 5485e925e18d..99755fc1a161 100644 --- a/drivers/crypto/inside-secure/safexcel.c +++ b/drivers/crypto/inside-secure/safexcel.c @@ -328,7 +328,7 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv) /* DMA transfer size to use */ val = EIP197_HIA_DSE_CFG_DIS_DEBUG; val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8); - val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS); + val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS); writel(val, priv->base + EIP197_HIA_DSE_CFG); /* Leave the DSE threads reset state */ |