diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-09-18 20:03:31 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-30 17:15:12 +0200 |
| commit | 36c0d0cf33ed31fada15caac34d50555b33208bb (patch) | |
| tree | 21dc2f7df14c241aae0c31a3f7957b37bc846d20 | |
| parent | eede3b53e9b5f7587e876ae9575392f92932951a (diff) | |
drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8e4fb80497a1..e7a3c1b4fc56 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2050,9 +2050,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); /* Workaround: set timing override bit. */ - val = I915_READ(_TRANSA_CHICKEN2); + val = I915_READ(TRANS_CHICKEN2(PIPE_A)); val |= TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(_TRANSA_CHICKEN2, val); + I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); val = TRANS_ENABLE; pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); @@ -2110,9 +2110,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) DRM_ERROR("Failed to disable PCH transcoder\n"); /* Workaround: clear timing override bit. */ - val = I915_READ(_TRANSA_CHICKEN2); + val = I915_READ(TRANS_CHICKEN2(PIPE_A)); val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(_TRANSA_CHICKEN2, val); + I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); } /** diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9643a7c433d8..cb409c2f7860 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6640,8 +6640,8 @@ static void lpt_init_clock_gating(struct drm_device *dev) PCH_LP_PARTITION_LEVEL_DISABLE); /* WADPOClockGatingDisable:hsw */ - I915_WRITE(_TRANSA_CHICKEN1, - I915_READ(_TRANSA_CHICKEN1) | + I915_WRITE(TRANS_CHICKEN1(PIPE_A), + I915_READ(TRANS_CHICKEN1(PIPE_A)) | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); } |