diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2020-03-13 12:01:04 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-06 18:43:24 +0200 |
| commit | 35509737c8f958944e059d501255a0bf18361ba0 (patch) | |
| tree | 08e54f009af1643ca6e322760165c84242a100a2 | |
| parent | 38743e414e7cc6d23f41276f298ad4781890a89f (diff) | |
ARM: tegra: Correct PL310 Auxiliary Control Register initialization
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.
This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:
L2C-310: enabling full line of zeros but not enabled in Cortex-A9
Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index f1ce2857a251..b620b0651157 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -107,8 +107,8 @@ static const char * const tegra_dt_board_compat[] = { }; DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") - .l2c_aux_val = 0x3c400001, - .l2c_aux_mask = 0xc20fc3fe, + .l2c_aux_val = 0x3c400000, + .l2c_aux_mask = 0xc20fc3ff, .smp = smp_ops(tegra_smp_ops), .map_io = tegra_map_common_io, .init_early = tegra_init_early, |