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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-10-31 18:12:49 -0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 23:51:24 +0100
commit25f3ef11cda25c71e14011990f6ad5e587c3c214 (patch)
treee02c2931239d9c553af52b63db8b63fd434e482d
parent937bb610b2b4c99946260cd64ab3cb562ec41b65 (diff)
drm/i915: don't rely on previous values when setting LPT TRANSCONF
Because we already set all the bits we can set. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: apply by hand due to dropped patch. Also, obey my OCD a bit and do a s/_TRANSACONF/TRANSCONF(TRANSCODER_A)/, makes it more consisten with other lpt pch code imnsho ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9c25199a5e4a..43ad1a556b3c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1729,16 +1729,15 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
- val = I915_READ(_TRANSACONF);
+ val = TRANS_ENABLE;
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
- val &= ~TRANS_INTERLACE_MASK;
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
val |= TRANS_INTERLACED;
else
val |= TRANS_PROGRESSIVE;
- I915_WRITE(_TRANSACONF, val | TRANS_ENABLE);
+ I915_WRITE(TRANSCONF(TRANSCODER_A), val);
if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("Failed to enable PCH transcoder\n");
}