diff options
| author | Charles Keepax <ckeepax@opensource.cirrus.com> | 2021-05-10 14:13:53 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-05-10 17:27:51 +0100 |
| commit | 1a46b7b82df57b6b6a4e891cdbb2de1cf818a43b (patch) | |
| tree | 4aeb99168e47feac35049d7b5ef880798bdc2aeb | |
| parent | 60ba916d87600684a1e127b484e1c407c355caad (diff) | |
ASoC: cs35l35: Correct errata handling
Currently the check of errata_chk will always evaluate to false since
the values tested don't come under the mask used. A shift of the field
is missing, add this. Also there is an error in the values tested, they
don't match the comment and the value 0x3 is not a valid value for the
field in question. Update the value to match the comment.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210510131357.17170-7-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/cs35l35.c | 4 | ||||
| -rw-r--r-- | sound/soc/codecs/cs35l35.h | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/sound/soc/codecs/cs35l35.c b/sound/soc/codecs/cs35l35.c index 554b32f388d9..a4309312e84f 100644 --- a/sound/soc/codecs/cs35l35.c +++ b/sound/soc/codecs/cs35l35.c @@ -496,10 +496,10 @@ static int cs35l35_hw_params(struct snd_pcm_substream *substream, * the Class H algorithm does not enable weak-drive operation for * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10 */ - errata_chk = clk_ctl & CS35L35_SP_RATE_MASK; + errata_chk = (clk_ctl & CS35L35_SP_RATE_MASK) >> CS35L35_SP_RATE_SHIFT; if (classh->classh_wk_fet_disable == 0x00 && - (errata_chk == 0x01 || errata_chk == 0x03)) { + (errata_chk == 0x01 || errata_chk == 0x02)) { ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DEL_MASK, diff --git a/sound/soc/codecs/cs35l35.h b/sound/soc/codecs/cs35l35.h index ffb154cd962c..2117dcb08c46 100644 --- a/sound/soc/codecs/cs35l35.h +++ b/sound/soc/codecs/cs35l35.h @@ -168,6 +168,7 @@ #define CS35L35_SP_SCLKS_48FS 0x0B #define CS35L35_SP_SCLKS_64FS 0x0F #define CS35L35_SP_RATE_MASK 0xC0 +#define CS35L35_SP_RATE_SHIFT 6 #define CS35L35_PDN_BST_MASK 0x06 #define CS35L35_PDN_BST_FETON_SHIFT 1 |