diff options
| author | Roger Quadros <rogerq@ti.com> | 2013-06-18 19:04:46 +0300 |
|---|---|---|
| committer | Benoit Cousson <benoit.cousson@linaro.org> | 2013-06-19 16:59:28 -0500 |
| commit | 153030c22defea2f96546d0f1a74fe954551c4cd (patch) | |
| tree | b7032d748202c494896936d2f3631242edc85d44 | |
| parent | 6f56929375be006e114fe5be09095b1ff3edfb99 (diff) | |
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
USB Host PHY clock on port 2 must be configured to 19.2MHz.
Provide this information.
Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/omap5-uevm.dts | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 30adeaf47883..08b72678abff 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -42,6 +42,13 @@ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; reset-supply = <&hsusb2_reset>; + /** + * FIXME + * Put the right clock phandle here when available + * clocks = <&auxclk1>; + * clock-names = "main_clk"; + */ + clock-frequency = <19200000>; }; /* HS USB Port 3 RESET */ |