diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2019-05-02 23:25:02 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-06-07 11:49:01 -0700 |
| commit | 13ad1948d90d139437257d73622735d0f075777e (patch) | |
| tree | cc562edccdbd0d0eaa042e3f9a14fdfd6508b61b | |
| parent | 74054c413ae8c36a5529e7891c2450a747667753 (diff) | |
clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly
The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.
Restore the correct behaviour using the newly introduced .div_table
field.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/ingenic/jz4725b-cgu.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 31325dd40a0f..47287956824b 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -37,6 +37,10 @@ static const u8 jz4725b_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, }; +static const u8 jz4725b_cgu_pll_half_div_table[] = { + 2, 1, +}; + static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { /* External clocks */ @@ -70,7 +74,10 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, + jz4725b_cgu_pll_half_div_table, + }, }, [JZ4725B_CLK_CCLK] = { |