diff options
| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2006-06-20 23:26:30 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-06-29 21:10:51 +0100 |
| commit | 08aecfb9eaf019f07384175101c970ede271c17a (patch) | |
| tree | ddce36622b5c408f9e4d8e03b7ef72c9c9cb681a | |
| parent | 1500b9a0f4381831e41f7e02f61dbef980ded342 (diff) | |
[MIPS] Remove set_c0_status(ST0_IM) from wrppmc's irq.c.
mips_cpu_irq_init() does clear_c0_status(ST0_IM) first, so
set_c0_status(ST0_IM) isn't necessary.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/gt64120/wrppmc/irq.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 26cf360f1694..8d75a43ce877 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -62,9 +62,6 @@ void gt64120_init_pic(void) void __init arch_init_irq(void) { - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0 */ - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ mips_cpu_irq_init(0); |