From 39490552f2a84282143e0ec039fdaf4b2f309539 Mon Sep 17 00:00:00 2001 From: Pete Johanson Date: Wed, 30 Dec 2020 15:44:03 -0500 Subject: feat(boards): Add BDN9 Rev2 board. * Onboard stm32f072. * 3 possible encoder positions. * Underglow/per-key not yet support. --- app/boards/arm/bdn9/bdn9_rev2_defconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 app/boards/arm/bdn9/bdn9_rev2_defconfig (limited to 'app/boards/arm/bdn9/bdn9_rev2_defconfig') diff --git a/app/boards/arm/bdn9/bdn9_rev2_defconfig b/app/boards/arm/bdn9/bdn9_rev2_defconfig new file mode 100644 index 0000000..139cf85 --- /dev/null +++ b/app/boards/arm/bdn9/bdn9_rev2_defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: MIT + +CONFIG_SOC_SERIES_STM32F0X=y +CONFIG_SOC_STM32F072XB=y +# 72MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 + +# Floating Point Options +CONFIG_FPU=y + +# enable GPIO +CONFIG_GPIO=y + +# Needed to reduce this to size that will fit on F072 +CONFIG_HEAP_MEM_POOL_SIZE=1024 + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# Clock configuration for Cube Clock control driver +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y +# use HSI as PLL input +CONFIG_CLOCK_STM32_PLL_SRC_HSI=y +# produce 72MHz clock at PLL output +CONFIG_CLOCK_STM32_PLL_PREDIV=1 +CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=2 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 -- cgit v1.2.3