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| author | CrossR <r.cross@lancaster.ac.uk> | 2020-08-21 22:03:52 +0100 |
|---|---|---|
| committer | CrossR <r.cross@lancaster.ac.uk> | 2020-08-21 22:03:52 +0100 |
| commit | 84761fc58931c8caa8cf1bf1b39946a9cb652822 (patch) | |
| tree | ab5effc50925021507f742ed8206fbd683f4ee99 /app/boards/arm/nrfmicro/nrfmicro_13_defconfig | |
| parent | 5c29259fedc4a0265064afc0bc141e6bf33425f2 (diff) | |
| parent | c619fb9c58c8f2dbcc19d74e7502459b49633113 (diff) | |
Merge branch 'main' into CrossR/Sofle
Diffstat (limited to 'app/boards/arm/nrfmicro/nrfmicro_13_defconfig')
| -rw-r--r-- | app/boards/arm/nrfmicro/nrfmicro_13_defconfig | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/app/boards/arm/nrfmicro/nrfmicro_13_defconfig b/app/boards/arm/nrfmicro/nrfmicro_13_defconfig new file mode 100644 index 0000000..cac1164 --- /dev/null +++ b/app/boards/arm/nrfmicro/nrfmicro_13_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT + +CONFIG_SOC_SERIES_NRF52X=y +CONFIG_SOC_NRF52840_QIAA=y +CONFIG_BOARD_NRFMICRO_13=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_MPU_ALLOW_FLASH_WRITE=y +CONFIG_NVS=y +CONFIG_SETTINGS_NVS=y +CONFIG_FLASH=y +CONFIG_FLASH_PAGE_LAYOUT=y +CONFIG_FLASH_MAP=y +CONFIG_CLOCK_CONTROL_NRF=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y |